Arun Basil Paul

--- Über mich

Arun Basil Paul

Hallo, ich habe einen Masterabschluss in Mechatronik mit Schwerpunkt Eingebettete Systeme. Ich erstelle Projekte, die Menschen helfen und die Effizienz eingebetteter Systeme durch Hardwarebeschleunigung, benutzerdefinierte Betriebssystementwicklung, IP-Erstellung usw. verbessern. Schauen Sie sich gerne meine Projekte an und kontaktieren Sie mich.

Stadt: Siegen -> Munich LinkedIn: www.linkedin.com/in/arun-basil-paul

Grad: Masters in Mechatronics Universität: Universität Siegen

Spezialisierung: Eingebettete Systeme Email: arunbasilpaul@gmail.com

Arbeit : Suchen GitHub: www.github.com/arunbasilpaul

--- About Me

Arun Basil Paul

Hello, I'm a graduate with a Master's in Mechatronics specialising in Embedded Systems. I create projects that help people and improve efficiency in Embedded systems through Hardware acceleration, custom OS development, IP creation, etc. Feel free to check out my projects and reach out.

City

Degree

University

Specialization

Email

Job

GitHub

LinkedIn

Siegen -> Munich

Masters in Mechatronics

Universität Siegen

Embedded Systems

arunbasilpaul@gmail.com

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www.github.com/arunbasilpaul

www.linkedin.com/in/arun-basil-paul

--- Was ich weiss
Universität Siegen, Siegen

Grad: Masters in Mechatronics

Interessante Themen: FPGA | Eingebettete Systeme | VHDL | Verilog | Verifizierung | Leistungsoptimierung | Benutzerdefinierte IP-Erstellung | Hardwarebasiertes Betriebssystem | Maschinelles Lernen | Hardwarebeschleunigung

NMAMIT, India

Grad: Bachelor in Maschinenbau

Interessante Themen: Mechatronik | PLC-Programmierung | Hardware praktisch | Thermodynamik | Maschinenzeichnung | CAD-Tools | Löten | C++-Programmierung | Maschinendynamik

--- What I know
Universität Siegen, Siegen

Degree: Masters in Mechatronics

Topics of interest: FPGA | Embedded Systems | VHDL | Verilog | Verification | Power Optimisation | Custom IP creation | Hardware based OS | Machine Learning | Hardware Acceleration

NMAMIT, India

Degree: Bachelors in Mechanical Engineering

Topics of interest: Mechatronics | PLC Programming | Hardware practical | Thermodynamics | Machine Drawing | CAD Tools | Soldering | C++ Programming | Machine dynamics

--- Wie ich es gemacht habe

Vivado | Vitis | HLS | TCL | PetaLinux | Linux(Ubuntu) | MATLAB | Simulink | Git | Oscilloskop

VHDL | Verilog | C++ | C | Eingebettetes C | Grundlagen von Python und SystemVerilog

AXI | UART | I2C | SPI | Ethernet | CAN | LIN

RTL-Programmierung | Maschinelles Lernen | Benutzerdefinierte IPs | Speicheroptimierung | DO-254 | Hardwarebeschleunigung

TE0802 Zynq Ultrascale+ | Pynq Z1 | Pynq Z2 | Zedboard | ZCU102 | Zybo board

--- How I did

Vivado | Vitis | HLS | TCL | PetaLinux | Linux(Ubuntu) | MATLAB | Simulink | Git | Oscilloscope

TE0802 Zynq Ultrascale+ | Pynq Z1 | Pynq Z2 | Zedboard | ZCU102 | Zybo board

C | C++ | VHDL | Verilog | Embedded C | basics of Python and SystemVerilog

AXI | UART | I2C | SPI | Ethernet | CAN | LIN

RTL-Programming | Memory Optimisation | Custom IPs | Machine Learning | Hardware Acceleration | DO-254

--- Was ich habe gemacht
man with VR headset
man with VR headset

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Optimising Deep Learning model performance through the integration of a Time-Triggered Memory cache with Versatile Tensor Accelerator

Neural Network implementation on TE0802 Zynq Ultrascale+ using Vitis HLS

a red sign that is on the side of a building
a red sign that is on the side of a building

Development of custom Linux OS for TE0802 Zynq Ultrascale+ Board with TVM/VTA Interface

DRAM pattern analysis for VTA Load module schedule simplification

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02

text
text

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Alarm clock with LED display configuration

Traffic Light with Emergency provision during special circumstances

--- What I did
man with VR headset
man with VR headset

01

02

a red sign that is on the side of a building
a red sign that is on the side of a building
text
text

Optimising Deep Learning model performance through the integration of a Time-Triggered Memory cache with Versatile Tensor Accelerator

Neural Network implementation on TE0802 Zynq Ultrascale+ using Vitis HLS

01

02

Development of custom Linux OS for TE0802 Zynq Ultrascale+ Board with TVM/VTA Interface

DRAM pattern analysis for VTA Load module schedule simplification

01

02

Alarm clock with LED display configuration

Traffic Light with Emergency provision during special circumstances

--- Nehmen Sie Kontakt auf

„Vielen Dank für Ihren Besuch ... Mein Lebenslauf wurde hochgeladen. Schauen Sie sich gerne meine GitHub-Seite für neue Projekte an und schreiben Sie mir über meine E-Mail oder LinkedIn. Wenn Sie sich außerdem für Fotografie interessieren, schauen Sie sich meine Instagram-Seite an.“

--- Get in Touch

“Thank you for visiting .... My Resume has been uploaded. Feel free to check out my GitHub page for new projects and write to me through my E-mail or LinkedIn. Moreover, if you are interested in photography try my Instagram page”