alarm clock

alarm clock

This project implements a digital alarm clock using hardware description languages (HDLs), specifically VHDL and Verilog. The clock counts seconds, minutes, and hours, and supports an alarm function that triggers based on preset values. Time and alarm values are displayed using 7-segment displays. The design is suitable for FPGA-based implementations and serves as a fundamental example of digital logic design.

Features

• Time Counting: Counts up to 60 seconds, 60 minutes, and 24 hours, displaying the time using 7-segment displays.

• Alarm Functionality: The alarm can be set to trigger at a specific time. When the time matches the preset alarm value, an alarm signal is activated.

• 7-Segment Display: Current time and alarm values are displayed on 7-segment displays, broken down into ones and tens for each unit (seconds, minutes, hours)

Tools & Technologies

• HDLs: VHDL and Verilog

• Simulation: Testbenches written in both VHDL and Verilog for simulation purposes.

Development Process

• Design Specification: Outlined the functional requirements for the alarm clock, including timekeeping and alarm triggering mechanisms.

• Module Development: Developed individual modules for time counting, alarm comparison, and 7-segment display control.

• Simulation & Testing: Created testbenches to simulate and verify the functionality of each module.

• Integration: Integrated modules into a cohesive system, ensuring proper communication and synchronization between components.

• Deployment: Prepared the design for FPGA implementation, considering resource utilization and timing constraints.

Challenges & Solutions

• Time Synchronization: Ensuring accurate timekeeping required careful management of clock signals and counters.

  • Solution: Implemented precise clock division and synchronization techniques to maintain accurate time increments.

• Display Multiplexing: Controlling multiple 7-segment displays with limited I/O pins posed a challenge.

  • Solution: Utilized multiplexing strategies to efficiently drive multiple displays using shared control lines.

Result

The project successfully demonstrates the implementation of a digital alarm clock using HDLs, suitable for FPGA deployment. It serves as a foundational example for understanding digital design principles and hardware implementation.

TRAFFIC LIGHTS

traffic lights

Designed and implemented a traffic light controller using digital logic principles in VHDL. The system mimics a real-world intersection by controlling lights for vehicles and pedestrians with proper sequencing and delays, including pedestrian crossing requests.

Features

• Realistic Signal Timing: Implements green, yellow, and red light durations similar to actual road intersections.

• Pedestrian Button: Incorporates a pedestrian request button that safely interrupts the vehicle flow.

• Synchronous Design: Based on a finite state machine (FSM) with clean state transitions and reliable timing.

• LED Output Simulation: Visual output provided through simulation

Tools & Technologies

• HDL: VHDL

• Simulation: ModelSim

Development Process

• FSM Design: Defined clear states for traffic flow (Car_Green, Car_Yellow, Pedestrian_Green, etc.)

• Timing Logic: Implemented delay counters using clock division for proper signal timing.

• Input Handling: Designed a debounced pedestrian push-button input system.

• LED Mapping: Mapped FSM states to LEDs for visual feedback.

• Testing & Verification: Created testbenches to simulate and verify behavior of the FSM and timing logic.

Challenges & Solutions

• Accurate Delay Control: Managing time intervals with high precision using clock division.

  • Solution: Used counters driven by a 50 MHz clock to simulate real-time delays.

• Asynchronous Inputs: Handling unpredictable pedestrian requests without glitches.

  • Solution: Used synchronized edge detection for button presses and included debouncing logic.

Result

• Fully functional, deterministic traffic controller that can be implemented on FPGA boards.

• Serves as an educational project for FSM design, timing control, and embedded systems principles.

• Demonstrates real-world embedded system thinking in HDL.

fifo

fifo

This project demonstrates and compares Synchronous and Asynchronous FIFO (First-In-First-Out) memory designs using VHDL. FIFO buffers are essential in digital systems for managing data between processes running at different clock domains. This project showcases the architecture, implementation, and simulation of both FIFO types, highlighting differences in complexity, design strategies, and reliability.

Features

• Synchronous FIFO: Operates under a single clock domain.

• Asynchronous FIFO: Handles communication between two different clock domains using Gray code pointers and dual-port memory.

• Simulation Testbenches: Validates correctness, full/empty status, and pointer behavior under varying write/read rates.

• Comparative Architecture: Visual and logical contrast between sync and async designs.

Tools & Technologies

• HDL: VHDL

• Simulation: ModelSim or any compatible VHDL simulator

• Target Hardware: FPGA-based implementation supported (generic architecture)

• Design Methodologies: FSM, clock domain crossing, Gray code logic

Development Process

• FSM Design: Defined clear states for traffic flow (Car_Green, Car_Yellow, Pedestrian_Green, etc.)

• Timing Logic: Implemented delay counters using clock division for proper signal timing.

• Input Handling: Designed a debounced pedestrian push-button input system.

• LED Mapping: Mapped FSM states to LEDs for visual feedback.

• Testing & Verification: Created testbenches to simulate and verify behavior of the FSM and timing logic.

Challenges & Solutions

• Clock Domain Crossing (CDC) in Asynchronous FIFO
  Solution: Implemented pointer synchronization using double-register synchronizers and Gray code encoding to ensure reliable operation across domains.

• Overflow/Underflow Control
  Solution: Carefully designed logic for full and empty conditions, avoiding race conditions during simultaneous read/write.

Result

• Functional FIFO modules (sync and async) with simulation-backed validation.

• Educational comparison useful for understanding digital system buffering and CDC.

• Can be extended for DMA buffers, UART interfaces, or data streaming applications.

RTL IN NN

RTL IN NN

This project showcases the deployment of a simple neural network inference engine on the TE0802 Zynq Ultrascale+ FPGA development board. It aims to accelerate AI computations using FPGA-based custom hardware, enabling real-time digit classification on embedded systems. The platform bridges machine learning and hardware design for efficient edge inference, particularly in robotics and embedded AI applications.

Features

• Matrix multiplication engine for neural inference via custom HLS IP

• Memory-mapped BRAM interface for fast data handling

• UART-based communication to send input images from PC to FPGA

• LED output for visual representation of classification results

• Modular design: HLS-based compute core + VHDL-based control logic

• Bare-metal software for Zynq ARM core to orchestrate inference

Tools & Technologies

• Hardware Platform: TE0802 Zynq Ultrascale+

• Languages & Frameworks: C++, Python, VHDL, TensorFlow 2.6.0

• Tools: Xilinx Vivado 2021.1, Vitis HLS, Vitis IDE

• Communication: UART

• Memory Interfaces: AXI-Lite, BRAM

Development Process

• Neural Network Training

  • Trained a 3-layer neural network on the MNIST dataset using TensorFlow

  • Extracted weight and bias parameters for hardware use

• HLS IP Core Design

  • Implemented matrix multiplication in C++ and synthesized it into RTL using Vitis HLS

  • Defined AXI interfaces for control and data transfer

• Hardware Integration (Vivado)

  • Connected the HLS IP to the Zynq PS and BRAM via AXI

  • Designed additional control modules in VHDL: nn_ctrl.vhd, not_gate.vhd, fix_address.vhd

• Software Development (Vitis)

  • Wrote a bare-metal C application to transfer image data and initiate inference

  • Received classification result and used LEDs for output

• Testing & Debugging

  • Created Python scripts to send test images over UART

  • Validated inference accuracy and FPGA behavior

Challenges & Solutions

• Integrating HLS-generated IP into a custom FPGA system
  Solution:: Carefully configured AXI4-Lite and BRAM interfaces, and debugged using test benches and UART logs.

• Managing address space and data format for matrix input
  Solution:: Developed a custom VHDL module (fix_address.vhd) to standardize memory access alignment.

• Reliable PC-to-FPGA communication over UART
  Solution:: Implemented a robust handshaking protocol and error-checking in both Python and Vitis firmware.

Result

• Achieved real-time digit classification from MNIST using FPGA-accelerated inference

• Reduced latency and CPU load by offloading matrix computation to FPGA

• Created a modular and extendable template for deploying AI models on embedded hardware

• Educational value for understanding the end-to-end flow from ML model to custom hardware

pre-fetching

pre-fetching

This project demonstrates how to optimise a Deep Learning model on a Zynq Ultrascale+ board. The purpose was to create a first-aid device that would assist medical personnel in making accurate diagnoses and be reliable and instantaneous. A DL model was developed based on factors that include heart beat per second, blood pressure and temperature. An FPGA interface that could further optimise this system while ensuring accuracy was not compromised had to be developed.

Features

• Mapped ResNet-18 model: A ResNet-18 model was mapped for determining the time and addresses used for running the model.

• Schedules: Schedules were created for all the modules of the VTA architecture that could be used for future applications.

• Simulation and Verification: Simulated and verified the functionality of the model through Vivado Simulator and generated bitstream.

Tools & Technologies

• Mapping: DRAMSim2, Microsoft Excel

• Boards: Trenz TE0802 BSP from Trenz

• FPGA Toolchain: Xilinx Vivado / Vitis

• Embedded Linux Concept: Pre-fetching

Development Process

• Map the Resnet-18 Model

  • Using a Verification IP with a trigger that logs the time and addresses used by the model.

• Analyze the map for dependencies

  • Mapped the dependencies between the address that would signify delays on the model.

• Creation of schedules

  • Created schedules according to the requirements for the custom AXI Controller.

• Simulate the AXI Controller

  • Simulated the AXI Controller in Vivado to ensure proper functionality.

• Deployment

  • Generated bitstream for FPGA integration and application.

Challenges & Solutions

• Hardware Compatibility Issues
  Solution: Designed the VTA architecture and the custom AXI controller using HDL modules, using standard practices.

• Large Data mapping
  Solution: Used Microsoft Excel and Python to optimise patterns during the LOAD module.

Result

• Successfully booted and ran a custom PYNQ-enabled OS on the TE0802 board.

• Jupyter server accessible via IP, enabling web-based control of FPGA accelerators.

• Demonstrates advanced skills in embedded Linux, system customization, and FPGA software integration.

PATTERN RECONITION

PATTERN RECOGNITION

The purpose of this project was to demonstrate that there exists a specific pattern used by the Operating System during resource allocation, i.e. memory allocation.  The project encroached upon various patterns in the VTA architecture in the Load module.

Features

• Memory and time logging using Verification IP that can be reused for any process.

• Pattern recognition using Microsoft Excel to differentiate multiple patterns in a single pattern.

• Confirmation of pattern by simulating the pattern in Xilinx Vivado using pre-determined formulas.

Tools & Technologies

• Hardware Platform: TE0802 Zynq Ultrascale+

• Languages & Frameworks: VHDL, Verilog

• Tools: Xilinx Vivado 2021.1, Microsoft Excel

• Simulation: Xilinx Vivado

• Memory Interfaces: AXI-Full, BRAM

Development Process

• Logging time and memory

  • Using a custom Verification IP, the time and memory data were logged and transferred as an Excel file.

• Recognising pattern

  • Using built-in Microsoft Excel features and mapping techniques, an accumulation of patterns, usually in groups of two, was recognised and separated to further simplify.

• Simulation

  • The recognised patterns were converted into formulas.

  • VHDL and Verilog codes were created to display the patterns observed.

• Testing

  • The simulated patterns were checked with reference to the original patterns for verification.

Challenges & Solutions

• Memory overriding during data logging
  Solution:: The data had to be logged in multiple stages as more than 30000 data points were being logged.

• Pattern recognition
  Solution:: Multiple patterns assimilated into a single pattern and creating a standardised protocol provided the solution.

Result

• Recognised a set of patterns used by the Operating System during memory allocation.

• Identified protocols that can be used in the future to determine memory allocation patterns.

• Provided scope for pre-fetching projects.

pynq-linux os

pynq-linux os

This project demonstrates how to customize and deploy a PYNQ-based Linux OS for the Trenz TE0802 Zynq UltraScale+ MPSoC board using PetaLinux tools. The work involves tailoring the boot process, device trees, and root filesystem to support PYNQ features on custom hardware — a critical task for embedded developers building software-defined FPGA applications.

Features

• Custom Linux Build: Built a fully functional embedded Linux system from scratch using PetaLinux tools.

• PYNQ Compatibility: Integrated PYNQ overlays and Jupyter Notebook environment for hardware/software co-design.

• Board-Specific Integration: Adapted the OS to support the TE0802 board’s device tree, bootloader, and hardware configuration.

• Network & Peripheral Support: Verified support for SSH, Ethernet, serial console, and SD card booting.

Tools & Technologies

• PetaLinux: 2022.1 or compatible version

• FPGA Toolchain: Xilinx Vivado / Vitis

• Embedded Linux Concepts: u-boot, devicetree, rootfs, boot.bin, Jupyter over Python 3

Development Process

• Set Up PetaLinux Environment

  • Installed PetaLinux SDK and verified dependencies (Ubuntu, Python, tools).

• Imported Trenz BSP

  • Created a PetaLinux project using petalinux-create -t project and imported the TE0802 BSP.

• Device Tree & Config Customization

  • Modified system-user.dtsi and device tree to add hardware support for PYNQ-specific peripherals.

• Root Filesystem Expansion

  • Added required packages and Python libraries for Jupyter, NumPy, Matplotlib, etc.

• Build & Deploy

  • Generated boot files (BOOT.BIN, image.ub, rootfs) and deployed them to SD card for TE0802.

• Validation

  • Verified hardware access, SSH connectivity, and PYNQ overlay loading through Jupyter Notebook.

Challenges & Solutions

• Hardware Compatibility Issues
  Solution: Carefully aligned the device tree with Trenz TE0802 schematic and ensured matching u-boot config.

• PYNQ Package Integration
  Solution: Used Python3 virtual environments within rootfs and modified init.d scripts to autostart Jupyter server.

• Resource Constraints in RootFS
  Solution: Created a custom root filesystem image with selective Python dependencies to reduce bloat.

Result

• Successfully booted and ran a custom PYNQ-enabled OS on the TE0802 board.

• Jupyter server accessible via IP, enabling web-based control of FPGA accelerators.

• Demonstrates advanced skills in embedded Linux, system customization, and FPGA software integration.

drone painter

drone painter

This 100% Government-funded project aims to test the limit of utilising drones to paint high-rise buildings using a remote controller. Every year, thousands of people lose their lives working in dangerous conditions with little to no regard for safety. The project was devised as an alternative that provides a safer environment to these workers while ensuring job security by learning a simple set of remote-control instructions due to inbuilt safety protocols in the drone.

Features

• Safe working conditions: Built a drone-based project that offers little to no risks to the worker.

• Easy transformation: Simple training would enable the workers to become experts in operating the drone due to the in-built safety protocols in the drone.

• Increased efficiency: The system is 30% more efficient than any existing system.

• Easy reproduction: The system consists of simple parts and can be easily reproduced for mass production.

Tools & Technologies

• Frame: Tarot 650 Sports Frame

• Motors: 4114 320kV Brushless motor

• Propellers: 1655 Crabon Fibre propeller

• ESC: Opto ESC 40A

• Flight Controller: Pixhawk Cube

• Battery: 8000mAh 25C Battery

Development Process

• Develop the systems

  • In the initial phase, the three components: the drone, the painter, along with the paint supply systems and the connector to hold the drone and the paint system.

• Calculating the payload

  • Calculated the payload of the system to determine the drone parameters such as the Flight controller, wing diameter, motor power, Electronic Speed Controllers, and wiring.

• Ordering the components

  • The parts were ordered from the International market by grouping tenders, negotiation and approval from representatives.

• Assembling the paint system

  • The paint system was 3d printed, attached to the paint carrier and tested for optimum air pressure.

• Deploying the drone

  • The drone was calibrated, and the paint system was attached using a fixed connector for stable flight.

• Testing

  • The painting drone was tested and the details submitted to the Government of India.

Challenges & Solutions

• Component selection
  Solution: Extensive research and multiple negotiations with representatives from International markets provided insights.

• Paint mechanism
  Solution: Air-based paint was used for better efficiency and a longer lifespan of the drone due to fewer drops of paint falling back on the drone.

• Importing problems
  Solution: Some of the parts had to be constrained at the airport, and proper documentation was required to retrieve the parts. Remember to include the importing difficulty due to restrictions while looking for tenders in the International market.

Result

• Successfully created and provided a near-zero fatal solution to high-rise building painting.

• 30% improvement in system efficiency through air-based paint.

• Created a stable system through the efficient use of the Flight Controller.