--- Custom OS Development and Pattern Analysis
KEYWORDS:
Custom boards | Vivado | Vitis | PetaLinux | Pynq | Operating System | Deep Learning | ResNet
Developed the bitstream for the custom TE0802 Zynq Ultrascale+ board, ensuring optimal hardware configuration and performance.
Generated the Board Support Package (BSP) using PetaLinux and created a customized Pynq 2.6v image with integrated drivers and kernel modules.
Optimized a ResNet18 model on the newly built OS, enhancing performance, compatibility, and providing well-documented guidelines now used by students at the University of Siegen.
--- Custom OS Development and Pattern Analysis
KEYWORDS:
MakeFile | Vivado | Vitis | DRAM | Memory Optimisation | RTL | Memory Allocation and pages
Analyzed memory access patterns in DDR3 DRAM within the VTA architecture to identify key performance bottlenecks and improve data acquisition, processing and transfer.
Optimized memory access schedules for up to 3200 addresses, achieving efficiency with only 450 lines of code. Simulated and verified these schedules in Vivado and ModelSim, ensuring performance improvements.
Maintained detailed documentation to support the optimization and verification processes.
--- Custom OS Development and Pattern Analysis
KEYWORDS:
Custom boards | Vivado | Vitis | PetaLinux | Pynq | Operating System | Deep Learning | ResNet
Developed the bitstream for the custom TE0802 Zynq Ultrascale+ board, ensuring optimal hardware configuration and performance.
Generated the Board Support Package (BSP) using PetaLinux and created a customized Pynq 2.6v image with integrated drivers and kernel modules.
Optimized a ResNet18 model on the newly built OS, enhancing performance, compatibility, and providing well-documented guidelines now used by students at the University of Siegen.
--- Custom OS Development and Pattern Analysis
KEYWORDS:
MakeFile | Vivado | Vitis | DRAM | Memory Optimisation | RTL | Memory Allocation and pages
Analyzed memory access patterns in DDR3 DRAM within the VTA architecture to identify key performance bottlenecks and improve data acquisition, processing and transfer.
Optimized memory access schedules for up to 3200 addresses, achieving efficiency with only 450 lines of code. Simulated and verified these schedules in Vivado and ModelSim, ensuring performance improvements.
Maintained detailed documentation to support the optimization and verification processes.
