--- What I did

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Optimising Deep Learning model performance through the integration of a Time-Triggered Memory cache with Versatile Tensor Accelerator

Neural Network implementation on TE0802 Zynq Ultrascale+ using Vitis HLS

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Development of custom Linux OS for TE0802 Zynq Ultrascale+ Board with TVM/VTA Interface

DRAM pattern analysis for VTA Load module schedule simplification

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Alarm clock with LED display configuration

Traffic Light with Emergency provision during special circumstances