--- Deep Learning and Hardware Acceleration Projects
KEYWORDS:
Custom boards | Vivado | Vitis | PetaLinux | Pynq | Operating System | Deep Learning | ResNet
Developed the bitstream for the custom TE0802 Zynq Ultrascale+ board, ensuring optimal hardware configuration and performance.
Generated the Board Support Package (BSP) using PetaLinux and created a customized Pynq 2.6v image with integrated drivers and kernel modules.
Optimized a ResNet18 model on the newly built OS, enhancing performance, compatibility, and providing well-documented guidelines now used by students at the University of Siegen.
--- Deep Learning and Hardware Acceleration Projects
KEYWORDS:
Custom boards | Vivado | Vitis | PetaLinux | Pynq | Operating System | Deep Learning | ResNet
Developed the bitstream for the custom TE0802 Zynq Ultrascale+ board, ensuring optimal hardware configuration and performance.
Generated the Board Support Package (BSP) using PetaLinux and created a customized Pynq 2.6v image with integrated drivers and kernel modules.
Optimized a ResNet18 model on the newly built OS, enhancing performance, compatibility, and providing well-documented guidelines now used by students at the University of Siegen.
--- Deep Learning and Hardware Acceleration Projects
KEYWORDS:
Vivado | Vitis HLS | C++ | UART | Bitstream | Deep Learning
Generated an HLS project using template C++ files, customized parameters to match the network, and exported RTL to create the IP core.
Developed a Vivado project with tailored modules, generated the bitstream, exported hardware, and built a Vitis platform for deployment on the TE0802 board.
Utilized a test file for image validation via UART, verified outputs against test labels, and maintained documentation and version control to support seamless development and integration.
--- Deep Learning and Hardware Acceleration Projects
KEYWORDS:
Vivado | Vitis HLS | C++ | UART | Bitstream | Deep Learning
Generated an HLS project using template C++ files, customized parameters to match the network, and exported RTL to create the IP core.
Developed a Vivado project with tailored modules, generated the bitstream, exported hardware, and built a Vitis platform for deployment on the TE0802 board.
Utilized a test file for image validation via UART, verified outputs against test labels, and maintained documentation and version control to support seamless development and integration.
